| ADD | AND | ASR | BEQ | BMI | BNE |
| DEX | DEY | EOR | HLT | INA | INX |
| INY | JMP | JSR | LDA | LDM | LDS |
| LDX | LDY | LSL | LSR | MFC | MFS |
| MFX | MFY | MTC | MTS | MTX | MTY |
| MXY | MYX | NOP | ORA | OUT | PHA |
| PHX | PHY | PLA | PLX | PLY | ROL |
| ROR | RTS | SEQ | SLO | SLT | STM |
| SWP | SXS | SXY | SYS | TSR |
[destination] ← [source] + [destination]
ADD An, Am - $An0m
ADD An, #imm8 - $Bn00 + imm8 (1 byte)The immediate form takes 5 cycles, while the register form takes 4 cycles.
Add the source operand (Am or imm8) to the destination operand (An) and store the result in the destination location. C will be set to 1 if an overflow occurred, 0 if not.
[destination] ← [source] & [destination]
AND An, Am - $An2m
AND An, #imm8 - $Bn20 + imm8 (1 byte)The immediate form takes 5 cycles, while the register form takes 4 cycles.
AND the source operand (Am or imm8) to the destination operand (An) and store the result in the destination location.
[destination] ← [destination] shifted right by [source]
ASR An, Am - $An7m
ASR An, #0..7 - $Bn7iIn both cases, the minimum cycle time is 4 cycles, and the maximum is 11 cycles. The cycles required can be determined with the formula 4\+count where count is the shift amount.
Arithmetically shift the bits of the operand right. The shift count can be specified either as a literal from 0 to 7 (0 produces no shift), or in a register. If a register is used, the value is modulo 8. The bits in the operand are shifted into C.
IF C == 0 THEN [PC] ← [PC] + d
BEQ <label> - $C0 + rel8 (1 byte)If the branch is taken, the instruction takes 4 cycles. Otherwise, it takes only 3 cycles.
If the C register is zero, program execution continues at location [PC] + displacement, d. The displacement is a two's complement value. The value in the PC corresponds to the current location plus two. The range of the branch is -126 to +128 bytes.
IF C[7] == 1 THEN [PC] ← [PC] + d
BMI <label> - $C1 + rel8 (1 byte)If the branch is taken, the instruction takes 4 cycles. Otherwise, it takes only 3 cycles.
If bit 7 of C is set, program execution continues at location [PC] + displacement, d. The displacement is a two's complement value. The value in the PC corresponds to the current location plus two. The range of the branch is -126 to +128 bytes.
IF C != 0 THEN [PC] ← [PC] + d
BNE <label> - $C2 + rel8 (1 byte)If the branch is taken, the instruction takes 4 cycles. Otherwise, it takes only 3 cycles.
If the C register is not zero, program execution continues at location [PC] + displacement, d. The displacement is a two's complement value. The value in the PC corresponds to the current location plus two. The range of the branch is -126 to +128 bytes.
[X/Y] ← [X/Y] - 1
DEX - $F7
DEY - $F9Both DEX and DEY take 2 cycles.
Decrement X or Y by 1. The C register will be set to 0 if X/Y becomes zero after the operation, otherwise it is set to 0xFF implicitly.
[destination] ← [source] ^ [destination]
EOR An, Am - $An4m
EOR An, #imm8 - $Bn40 + imm8 (1 byte)The immediate form takes 5 cycles, while the register form takes 4 cycles.
EOR the source operand (Am or imm8) to the destination operand (An) and store the result in the destination location.
Halt the CPU
HLT - $FFHLT takes 2 cycles.
Halt the CPU until an interrupt is received. During this time, no instructions will be processed.
[destination] ← [I/O port]
INA An, Am - $An8m
INA An, #imm8 - $Bn80 + imm8 (1 byte)At minimum, INA will take 4 cycles to complete (5 cycles if using the immediate form). This number may be higher due to system design.
Read the value from the I/O port specified in the source operand (Am or imm8) into the destination operand (An)
[X/Y] ← [X/Y] + 1
INX - $F6
INY - $F8Both INX and INY take 2 cycles.
Increment X or Y by 1. The C register will be set to 0 if X/Y becomes zero after the operation, otherwise it is set to 0xFF implicitly.
[PC] ← [destination]
JMP <label> - $F3 + abs16 (2 bytes)JMP takes 4 cycles to complete.
Program execution continues at the effective address specified by the instruction.
[S] ← [S] - 2; M([S]) ← [PC]
[PC] ← [destination]
JSR <label> - $F4 + abs16 (2 bytes)JMP takes 7 cycles to complete.
JSR pushes the 16-bit address of the instruction immediately following the JSR onto the system stack. Program execution then continues at the effective address specified in the instruction.
[destination] ← [immediate literal]
LDA An, #imm8 - $8n + imm8 (1 byte)
LDX #imm16 - $F0 + imm16 (2 bytes)
LDY #imm16 - $F1 + imm16 (2 bytes)
LDS #imm16 - $F2 + imm16 (2 bytes)LDA takes 3 cycles to complete, while LDX/LDY/LDS take 5, due to the required additional fetch for the 16-bit literal.
Load the immediate literal specified into the destination.
[destination] ← M([source])
LDM An, [X] - $1n
LDM An, [Y] - $3n
LDM An, [S] - $5nLDM takes 4 cycles to complete.
Load the destination with the value at the memory address specified by the source.
[destination] ← [destination] shifted by [source]
LSL An, #0..7 - $An5m
LSL An, Am - $Bn5i
LSR An, #0..7 - $An6m
LSR An, Am - $Bn6iIn both cases, the minimum cycle time is 4 cycles, and the maximum is 11 cycles. The cycles required can be determined with the formula 4\+count where count is the shift amount.
Logically shift the bits of the operand in the specified direction. The shift count can be specified either as a literal from 0 to 7 (0 produces no shift), or in a register. If a register is used, the value is modulo 8. The bits in the operand are shifted into C.
[destination] ← [source]
MFC An - $En
MFX An - $FA0n
MFY An - $FA1n
MFS An - $FA2nMFC takes 2 cycles to complete, while MFX/MFY/MFS takes 4 cycles.
Copy the value of the source register into the destination. r specifies the source register:
| Mnemonic | Description |
|---|---|
| MFC | Move from C |
| MFX | Move from X |
| MFY | Move from Y |
| MFS | Move from S |
If r is X, Y, or S, the source operand will be copied into 2 registers, the low byte in the source operand (An) and the high byte in the register next to it (A(n+1)). If An is A15, the high byte will be in A0.
[source] ← [destination]
MTC An - $DN
MTX An - $FA3n
MTY An - $FA4n
MTS An - $FA5nMTC takes 2 cycles to complete, while MTX/MTY/MTS takes 4 cycles.
Write the value of the source register into the destination. r specifies the source register:
| Mnemonic | Description |
|---|---|
| MTC | Move to C |
| MTX | Move to X |
| MTY | Move to Y |
| MTS | Move to S |
If r is X, Y, or S, 2 registers will be used to perform the write, with the low byte in the source operand (An) and the high byte in the register next to it (A(n+1)) being written to the destination. If An is A15, the high byte will be in A0.
[Y] ← [X] / [X] ← [Y]
MXY - $FA60
MYX - $FA70Both MXY and MYX take 4 cycles to complete.
Copy the full contents of register X into Y (MXY), or register Y into X (MYX).
None
NOPNOP takes 2 cycles to complete.
NOP performs no operation. Execution continues with the instruction following the NOP instruction.
[destination] ← [source] | [destination]
ORA An, Am - $An3m
ORA An, #imm8 - $Bn30 + imm8 (1 byte)The immediate form takes 5 cycles, while the register form takes 4 cycles.
OR the source operand (Am or imm8) to the destination operand (An) and store the result in the destination location.
[I/O port] ← [destination]
OUT Am, An - $AnFm
OUT #imm8, An - $BnF0 + imm8 (1 byte)At minimum, OUT will take 4 cycles to complete (5 cycles if using the immediate form). This number may be higher due to system design.
Write the value from the I/O port specified in the source operand (Am or imm8) into the destination operand (An)
[S] ← [S] - 1; M([S]) ← [An] (PHA)
[S] ← [S] - 2; M([S]) ← [X/Y] (PHX/PHY)
PHA An - $4n
PHX - $FAE0
PHY - $FAE1PHA takes 3 cycles to complete, while PHX/PHY takes 6 cycles.
Push the 8-bit register (An) or 16-bit register (X/Y) onto the stack.
M([S]) → [An]; [S] ← [S] + 1 (PLA)
M([S]) → [X/Y]; [S] ← [S] + 2 (PLX/PLY)
PLA An - $9n
PLX - $FAF0
PLY - $FAF1PLA takes 3 cycles to complete, while PLX/PLY takes 6 cycles.
Pull an 8-bit value from the stack into An or a 16-bit value into X/Y.
[destination] ← [destination] rotated by [source]
ROL An, #0..7 - $AnCm
ROL An, Am - $BnCi
ROR An, #0..7 - $AnDm
ROR An, Am - $BnDiIn both cases, the minimum cycle time is 4 cycles, and the maximum is 11 cycles. The cycles required can be determined with the formula 4\+count where count is the shift amount.
Rotate the bits of the operand in the specified direction. The rotate operation is circular in the sense that the bit shifted out at one end is shifted into the other end, that is, no bit is lost or destroyed by a rotate operation. The shift count can be specified either as a literal from 0 to 7 (0 produces no rotation), or in a register. If a register is used, the value is modulo 8. The bits in the operand are shifted into C.
[PC] ← M([S]); [S] ← [S] + 2
RTSRTS takes 4 cycles to complete.
The program counter is pulled from the stack and the previous value of the PC is lost. RTS is used to terminate a subroutine.
IF [destination] == [source] THEN C ← 0x00 ELSE C ← 0xFF
SEQ An, Am - $An9m
SEQ An, #imm8 - $Bn90 + imm8 (1 byte)The immediate form takes 5 cycles, while the register form takes 4 cycles.
If the source (Am or imm8) is equal to the destination (An), C will be set to 0, otherwise it is set to 0xFF.
IF [destination] < [source] THEN C ← 0x00 ELSE C ← 0xFF
SLO An, Am - $AnBm
SLO An, #imm8 - $BnB0 + imm8 (1 byte)The immediate form takes 5 cycles, while the register form takes 4 cycles.
If the source (Am or imm8) is lower than the destination (An), C will be set to 0, otherwise it is set to 0xFF. Both operands are treated as unsigned operands.
IF [destination] < [source] THEN C ← 0x00 ELSE C ← 0xFF
SLT An, Am - $AnAm
SLT An, #imm8 - $BnA0 + imm8 (1 byte)The immediate form takes 5 cycles, while the register form takes 4 cycles.
If the source (Am or imm8) is less than the destination (An), C will be set to 0, otherwise it is set to 0xFF. Both operands are treated as signed operands.
M([destination]) ← [source]
STM An, [X] - $2n
STM An, [Y] - $7n
STM An, [S] - $6nSTM takes 3 cycles to complete.
Store the value from the source into memory at the memory address specified by the source.
[destination] ↔ [An:An+1]
SWP An, X - $FABn
SWP An, Y - $FACn
SWP An, S - $FADnSWP takes 4 cycles to complete.
Swap the contents of X/Y/S with a 16-bit value specified with the low byte in An and the high byte in the register next to it A(n+1). If An is A15, the high byte will be in A0.
[destination] ↔ [source]
SXY - $FA80
SXS - $FA90
SYS - $FAA0SXY/SXS/SYS takes 4 cycles to complete.
Exchange the contents of the destination and source together.
[destination] ← [source]
TSR An, Am - $AnEmTSR takes 4 cycles to complete.
Copy the source (Am) into the destination (An).